The present invention relates to a frequency synthesizer and, more particularly, to a frequency synthesizer having a phase locked loop (to be referred to as a PLL hereinafter).
The PLL is used to allow a voltage controlled oscillator (to be referred to as a VCO hereinafter) to oscillate at a predetermined frequency.
The PLL cannot oscillate over a wide frequency range if a slope KV of an F-V curve which indicates the relationship between a frequency F and control voltage Vctrl is small, i.e., if the gain is small.
Also, the F-V curve generally varies in accordance with, e.g., the temperature or manufacturing conditions. Therefore, the PLL cannot oscillate at a desired frequency or frequency range in some cases.
Furthermore, if the slope KV is small, the lockup time required before the PLL locks prolongs.
On the other hand, if the slope KV is increased, the stability of the PLL deteriorates. In addition, increasing the slope KV increases the current consumption and the apparatus area. Conventionally, therefore, increasing the slope KV is also a problem.
Moreover, the slope KV depends on the control voltage Vctrl. Therefore, if the control voltage Vctrl changes, the oscillation frequency F also changes, and this changes the slope KV. Accordingly, a frequency range in which oscillation within the range of the desired control voltage Vctrl is possible is narrow.
References disclosing the conventional frequency synthesizers are as follows.    1: Japanese Patent Laid-Open No. 2002-280901    2: U.S. Pat. No. 6,323,736    3: U.S. Pat. No. 6,388,536